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844008ay-16 1 rev. a january 15, 2008 ics844008-16 f emto c locks ? c rystal - to - lvds f requency s ynthesizer preliminary g eneral d escription the ics844008-16 is an 8 output lvds synthesizer optimized to generate pci express reference clock frequencies and is a member of the hiperclocks tm family of high performance clock solutions from idt. using a 25mhz parallel resonant crystal, the following frequencies can be generated based on f_sel pin: 100mhz or 125mhz. the ics844008-16 uses idt?s 3 rd generation low phase noise vco technology and can achieve <1ps typical rms phase jitter, easily meeting pci express jitter requirements. the ics844008-16 is packaged in a 32-pin lqfp package. f eatures eight lvds outputs crystal oscillator interface supports the following output frequencies: 100mhz or 125mhz vco: 500mhz rms phase jitter @ 125mhz, using a 25mhz crystal (1.875mhz - 20mhz): 0.44ps (typical) full 3.3v supply modes 0c to 70c ambient operating temperature available in both standard (rohs5) and lead-free (rohs 6) packages hiperclocks? ics p in a ssignment f requency s elect f unction t able 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 q0 nq0 v dd q1 nq1 gnd q2 nq2 mr nq4 q4 gnd v dd nq3 q3 f_sel v dda npll_sel v dd oe2 gnd xtal_out xtal_in oe1 ics844008-16 32-lead lqfp 7mm x 7mm x 1.4mm package body y package top view q7 nq7 v dd q6 nq6 gnd q5 nq5 1 0 phase detector vco 500mhz (w/25mhz reference) m = 20 (fixed) 4 5 osc b lock d iagram npll_sel xtal_in xtal_out oe1 mr f_sel oe2 q0 nq0 q1 nq1 q2 nq2 q3 nq3 q4 nq4 q5 nq5 q6 nq6 q7 nq7 pullup pullup 25mhz pulldown pullup pulldown tupni tuptuo ycneuqerf )zhm( tupni ycneuqerf )zhm (l es_f redividm eulav redividn eulav redividn/m eulav zhm5 200 24 5 5 21 zhm5 210 25 4 0 01 the preliminary information presented herein represents a product in pre-production. the noted characteristics are based on ini tial product characterization and/or qualification. integrated device technology, incorporated (idt) reserves the right to change any circui try or specifica- tions without notice.
844008ay-16 2 rev. a january 15, 2008 ics844008-16 f emto c locks ? c rystal - to - lvds f requency s ynthesizer preliminary t able 1. p in d escriptions t able 2. p in c haracteristics lobmy sr etemara ps noitidnoctse tm umini ml acipy tm umixa ms tinu c ni ecnaticapactupni 4f p r nwodllup rotsisernwodlluptupni 1 5k ? r pullup rotsiserpulluptupni 1 5k ? t able 3a. oe1 f unction t able tupn is tuptuo 1e o4 qn:0qn,4q:0q 0e tatsz-ihnistuptuosecalp 1n oitarepolamron t able 3b. oe2 f unction t able tupn is tuptuo 2e o7 qn:5qn,7q:5q 0e tatsz-ihnistuptuosecalp 1n oitarepolamron rebmu ne ma ne py tn oitpircsed 2, 10 qn,0 qt uptu o. slevelecafretnisdvl.riaptuptuolaitnereffid ,21,3 72,22 v dd rewo p. nipylppuseroc 5, 41 qn,1 qt upu o. slevelecafretnisdvl.riaptuptuolaitnereffid ,31,6 92,91 dn gr ewo p. dnuorgylppusrewop 8, 72 qn,2 qt uptu o. slevelecafretnisdvl.riaptuptuolaitnereffid 9l es_ ft upn ip ullu p. slevelecafretnilttvl/somcvlniptcelesycneuqerf 11,0 13 qn,3 qt uptu o. slevelecafretnisdvl.riaptuptuolaitnereffid 51,4 14 qn,4 qt uptu o. slevelecafretnisdvl.riaptuptuolaitnereffid 6 1r mt upni -dllup nwo tesererasredividlanretnieht,hgihcigolnehw.teserretsamhgihevitca xqnstuptuodetrevniehtdnawologotxqstuptuoeurtehtgnisuac erastuptuoehtdnasredividlanretnieht,wolcigolnehw.hgihogot .slevelecafretnilttvl/somcvl.delbane 81,7 15 q,5q nt uptu o. slevelecafretnisdvl.riaptuptuolaitnereffid 12,0 26 q,6q nt uptu o. slevelecafretnisdvl.riaptuptuolaitnereffid 42,3 27 q,7q nt uptu o. slevelecafretnisdvl.riaptuptuolaitnereffid 5 2v add rewo p. nipylppusgolana 6 2l es_llp nt upni -dllup nwo ,wolnehw.sredividehtottupnisaklc_ferdnallpehtneewtebstceles llp(kcolcecnereferehtstcelesed,hgihnehw.)elbanellp(llpstceles .slevelecafretnilttvl/somcvl.)ssapyb 8 22 e ot upn ip ullup .stuptuo7qn/7q:5qn/5qrofelbanetuptuo .slevelecafretnilttvl/somcvl 13,03 ,tuo_latx ni_latx tupni ,tuptuoehtsituo_latx.ecafretnilatsyrctnanoserlellarap .tupniehtsini_latx 2 31 e ot upn ip ullup .stuptuo4qn/4q:0qn/0qrofelbanetuptuo .slevelecafretnilttvl/somcvl :eton pullup .seulavlacipytrof,scitsiretcarahcnip,2elbatees.srotsisertupnilanretniotsrefer
844008ay-16 3 rev. a january 15, 2008 ics844008-16 f emto c locks ? c rystal - to - lvds f requency s ynthesizer preliminary t able 4a. p ower s upply dc c haracteristics , v dd = 3.3v5%, t a = 0c to 70c t able 4b. lvcmos / lvttl dc c haracteristics , v dd = 3.3v5%, t a = 0c to 70c a bsolute m aximum r atings supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, i o continuous current 10ma surge current 15ma package thermal impedance, ja 47.9c/w (0 lfpm) storage temperature, t stg -65c to 150c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of product at these conditions or any conditions be- yond those listed in the dc characteristics or ac character- istics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. lobmy sr etemara ps noitidnoctse tm umini ml acipy tm umixa ms tinu v hi egatlovhgihtupn iv dd v3.3 =2v dd 3.0 +v v li egatlovwoltupn iv dd v3.3 =3 .0 -8 . 0v i hi tupni tnerruchgih les_llpn,r mv dd v= ni 564.3 =0 5 1a les_f,2eo,1e ov dd v= ni 564.3 =5 a i li tupni tnerrucwol les_llpn,r mv dd v,v564.3= ni v0 =5 -a les_f,2eo,1e ov dd v,v564.3= ni v0 =0 51 -a t able 4c. lvds dc c haracteristics , v dd = 3.3v5%, t a = 0c to 70c lobmy sr etemara ps noitidnoctse tm umini ml acipy tm umixa ms tinu v do egatlovtuptuolaitnereffid 04 4v m ? v do v do egnahcedutingam 0 4v m v so egatlovtesffo 4. 1v ? v so v so egnahcedutingam 0 5v m lobmy sr etemara ps noitidnoctse tm umini ml acipy tm umixa ms tinu v dd egatlovylppuseroc 531. 33 . 35 64. 3v v add egatlovylppusgolana 531. 33 . 35 64. 3v i dd tnerrucylppusrewop 58 2a m i add tnerrucylppusgolana 2 1a m
844008ay-16 4 rev. a january 15, 2008 ics844008-16 f emto c locks ? c rystal - to - lvds f requency s ynthesizer preliminary t able 6. ac c haracteristics , v dd = 3.3v5%, t a = 0c to 70c t able 5. c rystal c haracteristics lobmy sr etemara ps noitidnoctse tm umini ml acipy tm umixa ms tinu f tuo ycneuqerftuptuo 0=les f5 2 1z hm 1=les f0 0 1z hm t )o(k s2 ,1eton;wekstuptuo db ts p t )cc(ti jr ettijelcyc-ot-elcyc 0 4s p t )?(tij ;)modnar(rettijesahpsmr 3eton )zhm02-zhm578.1(,zhm52 14 4. 0s p )zhm02-zhm578.1(,zhm00 14 4. 0s p t r t/ f emitllaf/esirtuptu o% 08ot%0 20 5 4s p cd oe lcycytudtuptuo 0 5% .snoitidnocdaollauqehtiwdnasegatlovylppusemasehttastuptuoneewtebwekssadenifed:1eton vtaderusaem dd .2/ .56dradnatscedejhtiwecnadroccanidenifedsiretemarapsiht:2eton .tolpesionesahpehtotreferesaelp:3eton retemara ps noitidnoctse tm umini ml acipy tm umixa ms tinu noitallicsofoedom latnemadnuf ycneuqerf 4.2 25 22 .7 2z hm 1eton;)mpp(noillimrepstrap 00 1m pp )rse(ecnatsiserseirestnelaviuqe 05 ? ecnaticapactnuhs 7f p levelevird 00 1w .latsyrctnanoserlellarapfp81nagnisudeziretcarahc:eton .draobcpresurofdetsujdaspacmirtlanretxednalatsyrcmpp05dednemmocerhtiwdesunehw:1eton
844008ay-16 5 rev. a january 15, 2008 ics844008-16 f emto c locks ? c rystal - to - lvds f requency s ynthesizer preliminary t ypical p hase n oise at 125mh z a t 3.3v 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 125mhz rms phase jitter (random) 1.875mhz to 20mhz = 0.44ps (typical) o ffset f requency (h z ) 1k 10k 100k 1m 10m 100m dbc hz n oise p ower ? ? ? raw phase noise data phase noise result by adding pci express filter to raw data pci express jitter filter
844008ay-16 6 rev. a january 15, 2008 ics844008-16 f emto c locks ? c rystal - to - lvds f requency s ynthesizer preliminary p arameter m easurement i nformation rms p hase j itter 3.3v c ore /3.3v o utput l oad ac t est c ircuit t sk(o) qy qx nqy nqx phase noise mas k offset frequency f 1 f 2 phase noise plot rms jitter = area under the masked phase noise plot noise power t pw t period t pw t period odc = x 100% q0:q7 nq0:nq7 c ycle - to -c ycle j itter o utput s kew scope qx nqx lvds 3.3v5% power supply +- float gnd o utput r ise /f all t ime o utput d uty c ycle /p ulse w idth /p eriod ? ? ? ? q0:nq7 nq0:nq7 t jit(cc) = t cycle n ? t cycle n+1 1000 cycles t cycle n t cycle n+1 clock outputs 20% 80% 80% 20% t r t f v swing o ffset v oltage s etup out out lv d s dc input ? ? ? v os / v os v dd d ifferential o utput v oltage s etup ? ? ? 100 out out lv d s dc input v od / v od v dd
844008ay-16 7 rev. a january 15, 2008 ics844008-16 f emto c locks ? c rystal - to - lvds f requency s ynthesizer preliminary c rystal i nput i nterface the ics844008-16 has been characterized with 18pf parallel resonant crystals. the capacitor values shown in figure 2. c rystal i npu t i nterface figure 2 below were determined using a 25mhz parallel resonant crystal and were chosen to minimize the ppm error. a pplication i nformation as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. the ics844008-16 pro- vides separate power supplies to isolate any high switch- ing noise from the outputs to the internal pll. v dd and v dda should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. to achieve optimum jitter performance, power supply isolation is required. figure 1 illustrates how a 10 ? resistor along with a 10f and a .01 f bypass capacitor should be connected to each v dda . p ower s upply f iltering t echniques f igure 1. p ower s upply f iltering 10 ? v dda 10 f .01 f 3.3v .01 f v dd c1 27p x1 18pf parallel crystal c2 27p xtal_out xtal_in
844008ay-16 8 rev. a january 15, 2008 ics844008-16 f emto c locks ? c rystal - to - lvds f requency s ynthesizer preliminary f igure 3. t ypical lvds d river t ermination 3.3v lvds d river t ermination a general lvds interface is shown in figure 3. in a 100 ? differential transmission line environment, lvds drivers require a matched load termination of 100? across near the receiver input. for a multiple lvds outputs buffer, if only partial outputs are used, it is recommended to termi- nate the unused outputs. r1 100 3. 3v 100 ohm differential transmission line 3. 3v + - lvds i nputs : lvcmos c ontrol p ins : all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. r ecommendations for u nused i nput and o utput p ins o utputs : lvds all unused lvds output pairs can be either left floating or terminated with 100 ? across. if they are left floating, we recommend that there is no trace attached.
844008ay-16 9 rev. a january 15, 2008 ics844008-16 f emto c locks ? c rystal - to - lvds f requency s ynthesizer preliminary p ower c onsiderations this section provides information on power dissipation and junction temperature for the ics844008-16. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics844008-16 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v dd = 3.3v + 5% = 3.465v, which gives worst case results. ? power (core) max = v dd_max * (i dd_max + i dda_max ) = 3.465v * (285ma + 12ma) = 1029mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks tm devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1c/w per table 7 below. therefore, tj for an ambient temperature of 70c with all outputs switching is: 70c + 1.029w * 42.1c/w = 113.3c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). t able 7. t hermal r esistance ? ? ja for 32-l ead lqfp, f orced c onvection ? ? ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 67.8c/w 55.9c/w 50.1c/w multi-layer pcb, jedec standard test boards 47.9c/w 42.1c/w 39.4c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs.
844008ay-16 10 rev. a january 15, 2008 ics844008-16 f emto c locks ? c rystal - to - lvds f requency s ynthesizer preliminary r eliability i nformation t ransistor c ount the transistor count for ics844008-16 is: 2597 t able 8. ja vs . a ir f low t able for 32 l ead lqfp ? ? ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 67.8c/w 55.9c/w 50.1c/w multi-layer pcb, jedec standard test boards 47.9c/w 42.1c/w 39.4c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs.
844008ay-16 11 rev. a january 15, 2008 ics844008-16 f emto c locks ? c rystal - to - lvds f requency s ynthesizer preliminary p ackage o utline - y s uffix for 32 l ead lqfp t able 9. p ackage d imensions reference document: jedec publication 95, ms-026 noitairavcedej sretemillimnisnoisnemidlla lobmys abb mumini ml animo nm umixam n 23 a - -- -0 6.1 1a 50. 0- -5 1.0 2a 53. 10 4. 15 4.1 b 03. 07 3. 05 4.0 c 90. 0- -0 2.0 d cisab00.9 1d cisab00.7 2d .fer06.5 e cisab00.9 1e cisab00.7 2e .fer06.5 e cisab08.0 l 54. 00 6. 05 7.0 ? ? 0 -- 7 ccc - -- -0 1.0
844008ay-16 12 rev. a january 15, 2008 ics844008-16 f emto c locks ? c rystal - to - lvds f requency s ynthesizer preliminary t able 10. o rdering i nformation rebmunredro/tra pg nikra me gakca pg nigakcapgnippih se rutarepmet 61-ya800448sc i6 1a800448sc ip fqldael2 3e bu tc 07otc0 t61-ya800448sc i6 1a800448sc ip fqldael2 3l eer&epat000 1c 07otc0 fl61-ya800448sc il 61a80044sc ip fql"eerf-dael"dael2 3e bu tc 07otc0 tfl61-ya800448sc il 61a80044sc ip fql"eerf-dael"dael2 3l eer&epat000 1c 07otc0 .tnailpmocshoreradnanoitarugifnoceerf-bpehterarebmuntrapehtotxiffus"fl"nahtiwderedroeratahtstrap:eton while the information presented herein has been checked for both accur acy and reliability, integrated de vice technology, incorp orated (idt) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not authorize or w arrant any idt product for use in life support devices or critical medical instruments.

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